1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as microcomputers having input/output ports through which data are transferred between the semiconductor integrated circuit of the present invention and other circuits mounted on other semiconductor chips and a fabrication method of the semiconductor integrated circuit.
2. Description of Related Art
FIGS. 1A and 1B are diagrams each showing a layout of semiconductor elements (only one is shown in each of the diagrams for brevity) and leads connected to lead frames in a conventional semiconductor integrated circuit having conventional input/output ports (hereinafter, referred to only as "ports"). In FIGS. 1A and 1B, the reference number 1 designates a semiconductor element (hereinafter, referred to as "a semiconductor chip"), 21 to 25 denote pad driver cells, each pad driver cell includes a pad and an output driver, the reference character IOC indicates an input/output control circuit region in which input/output control circuits are formed in the semiconductor chip 1, LIN denotes wiring region in which wirings are formed between the input/output control circuits and the pad driver cells 21 to 25, and PDR designates cell regions in which the PAD driver cells are formed. In FIGS. 1A and 1B, there are pad driver cells which are designated by no reference numbers for brevity.
The reference numbers 61 to 65 designate leads made from gold wires or aluminum wires connecting the pad driver cells 21 to 25 with corresponding lead frames. In FIGS. 1A and 1B, there are leads designated by no reference numbers. The reference number 200 designates a region in which no pad driver cell is formed.
In general, each semiconductor integrated circuit such as a micro-computer and the like is sealed with a plastic package or a ceramic package in order to protect the semiconductor integrated circuit from damages.
There are many kinds of packages which are different from each other in shape and in terminal number (or in pin number). Requirement in application and cost selects a package shape and the number of terminals.
However, because it takes much time and a lot of cost to develop semiconductor integrated circuits, it is difficult to prepare packages in which the number of terminals in each package is correspond to a semiconductor integrated circuit and it is also difficult to provide semiconductor integrated circuits whose shapes are different. Specifically, there are many user's requirements in order to obtain semiconductor integrated circuits having many port terminals and to use semiconductor integrated circuits in which the number of terminals is decreased in order to reduce implementing area.
FIGS. 1A and 1B show semiconductor chips 1-1 and 1-2 and leads 61 and 65 in two types of semiconductor circuits whose shapes and areas are same to each other but whose terminal numbers are different. Specifically, FIG. 1A shows the semiconductor integrated circuit having 24 pins and FIG. 1B shows the semiconductor integrated circuit having 20 pins.
FIG. 2 is a circuit diagram showing a circuit configuration of each of pad driver cells 21 to 25. In FIG. 2, the reference number 31 designates a P-channel MOS transistor whose source is connected to a power source and whose drain is connected to both a pad 30 and an input wire IN of an input/output control circuit. The reference number 32 denotes a N-channel MOS transistor whose drain is connected to the drain of the P-channel MOS transistor and whose drain is connected to the ground.
The gates of the P-channel and N-channel MOS transistors 31 and 32 are connected to output control wires CP and CN of the input/output control circuit, respectively. These P-channel and-N-channel MOS transistors form an output driver.
In addition, as shown by the dotted lines in FIG. 2, there is a case that the level of the input wire of the input/output control circuit is pulled up by the P-channel MOS transistor 33 whose operation is controlled by the level of a control signal transferred through a pull up control wire UC. In this case, the P-channel MOS transistor 31, the N-channel MOS transistor 32, and the P-channel MOS transistor 33 make up the input/output driver.
FIG. 3 is a block diagram showing an example of a configuration of the input/output control circuit. In the diagram, the reference number 41 designates a direction register for indicating a direction of a port, 42 denotes a port latch for latching output data transferred from a microcomputer through data buses, and 43 indicates a gate circuit which is open only when the port enters an input mode. The reference number 44 designates a pull-up control circuit for transferring a low level control signal through the pull up control wire UC only when the direction register 44 enters the input mode, 45 denotes an inverting AND circuit for outputting the inverted value of a value stored in the port latch 42 only when a value stored in the direction register 41 is "1", 46 indicates an inverting OR circuit for providing a value stored in the port latch 42 only when the value stored in the direction register is "1", and 47 indicates an inverter located between the direction register 41 and the inverting OR circuit 46. By the way, there is a case that no pull up circuit 44 is incorporated in the input/output control circuit designated by the dotted lines in FIG. 3.
A central processing unit (CPU) in the microcomputer sets "1" into the direction register 41 when the input/output control circuit enters an output mode, and sets "0" when an input mode.
When the value stored in the direction register 41 is "1", a level corresponding to data latched in the port latch 42 is transferred to the output control wires CP and CN. Then, the level corresponding to the data latched in the port latch 42 is transferred to a lead (a pin) in the semiconductor integrated circuit through the pad 30 and the lead frame.
On the other hand, when the value stored in the direction register 41 is "0", a level to set an off state to the P-channel and N-channel MOS transistors 31 and 32 is transferred to the output control wires CP and CN and the gate circuit 43 enters a signal passing state in which the signal is passing through the gate circuit 43. Thereby, the level of the signal received through a lead in the semiconductor integrated circuit is transferred to data buses. A port function in the semiconductor integrated circuit is achieved by using this input/output control circuit.
Next, a wiring method in the conventional semiconductor integrated circuit will now be explained.
Twenty four pad driver cells including the pad driver cells designated 21 to 25 are formed in the semiconductor chips 1-1 and 1-2, as shown in FIGS. 1A and 1B.
The all of the pad driver cells are wired to connect the pad driver cells with the corresponding lead frames in a 24 pin package such as the semiconductor chip 1-1. However, in a 20 pin package such as the semiconductor chip 1-2, there are the pad driver cells which are connected to no lead frame. These pad driver cells are allocated separately in the semiconductor chip, for example, allocated at every position of fourth pad driver cell.
Here, we assume that the pad driver cells 21 to 25 are corresponding to the ports A0 to A4, respectively, in order. In the example shown in FIG. 1B, the pad driver cell 22 has no wiring. In this case, there is no port A1 in the 20 pin package. That is, there are only ports A0, A2, A3 and A4 as the terminals of the semiconductor integrated circuit. We consider the shape of the semiconductor integrated circuit including the entire pad driver cells including them other than the pad driver cells 21 to 25. For example, in the 24 pin package, the ports A0 to A7, B0 to B7 are connected to the terminals of the semiconductor integrated circuit continuously. On the other hand, in the 20 pin package, only the ports A0 to A2, A4 to A6, B0 to B2, and B4 to B6 are connected to the terminals of the semiconductor integrated circuit.
We will now explain the above configuration in detail. The first case, namely the ports are connected to the terminals continuously, means that the terminals corresponding to the ports A0 to A7 are allocated to the first to eighth terminals which are placed continuously. When using the shape of the semiconductor integrated circuit 1-1 as the semiconductor integrated circuit 1-2, there is a disadvantage for 20 pin package users that ports can not be allocated per 4 bit unit or per 8 bit unit which is a basic unit for data processing in microcomputers. For example, in a case that the semiconductor integrated circuit is a microcomputer, programmers as users must develop programs while taking into serious consideration to ports allocated separately that can not be used.
In order to avoid the disadvantage in the conventional semiconductor integrated circuit described above, for example, it can be considered that the pad driver cells corresponding to the port B4 to B7 have no wirings so that the port A0 to A7 and B0 to B3 are connected to the terminals continuously. However, in this case, the positions of the pad driver cells having the wirings become offset. Because, each lead frame is allocated without offset, in general, this causes that there is a pad driver cell connected to a lead frame with a long wiring. However, when the length of a wiring becomes long, a lead is easier to connect electrically with a semiconductor substrate and the semiconductor chip 1-1, so that there is a limit, namely, it is difficult to connect a pad driver cell to a lead frame with a long wiring.
Accordingly, in a 20 pin package, pad driver cells that have no wirings must be allocated separately. In general, the recommended range of a length of a lead is determined every semiconductor integrated circuit fabrication companies.
FIGS. 4A and 4B are diagrams showing a layout of the input/output control circuits 11 to 15, the wiring region LIN, and the pad driver cells 21 to 25 when both a package having a large number of pins and a package having a small number of pins are formed by changing a semiconductor chip layout.
FIG. 4A shows a layout of a semiconductor chip having the large number of pins and FIG. 4B shows a layout of a semiconductor chip having the small number of pins.
When both semiconductor chips are compared in pin arrangement, the pad driver cells 21 to 25 are arranged closely in the semiconductor chip having the larger number of pins. On the other hand, the pad driver cells 21 to 25 are arranged roughly in the semiconductor chip having the small number of pins.
In the case that the input/output control circuits 11 to 15 shown in FIGS. 4A and 4B are corresponding to the ports A0 to A4, the input/output control circuits 11 and 15 are connected to pad driver cells corresponding to the port A0 and A4 (not shown) in the semiconductor chip having the small number of pins shown in FIG. 4B. The input/output control circuits 12, 13 and 14 are connected to the pad driver cells 21, 23 and 25, respectively. The pad driver cells (not shown) are connected to terminals corresponding to the ports A0 and A4 through the lead frames. The pad driver cells 21, 23 and 25 are connected to the terminals corresponding to the ports A1, A2 and A3, respectively.
By using the manner described above, the ports A0 to A4 are connected to terminals continuously in the semiconductor integrated circuit having the small number of pins. It can therefore be avoided that it is difficult to allocate ports every a four bit unit or every an eight bit unit.
However, it must be required to form a semiconductor fabrication mask used in each process in semiconductor chip fabrication processes which is different from a mask used in each process in them for the semiconductor chip having the large number of pins shown in FIG. 4A. In addition, there are many costs for fabricating the masks. Thus, it takes many times and much costs for fabricating semiconductor integrated circuits having chips corresponding to many types and shapes of packages.
The literature of the Laid open publication number: JP-A-59/145542 discloses a technique in which a plurality of input/output circuit sections and a plurality of pads are formed in a peripheral section in a semiconductor chip in order to apply many types of packages by changing wirings between each input/output circuit section and the each pad according to the terminal number of terminals in each package. However, this literature of JP-A-59/145542 described above does not disclose any actual manner for wirings between input/output circuit sections and pads.
Because the conventional semiconductor integrated circuit has the configuration described above, there is a drawback that it is difficult to allocate terminals corresponding to ports continuously when a semiconductor chip is sealed in other types of packages.
In addition, in the semiconductor integrated circuit, there is another drawback that each mask used for each of semiconductor fabrication processes for forming a semiconductor chip having a small number of pins must be changed when terminals corresponding to ports are arranged continuously.